Multi-dimensional-access memory system with combined data rotation and multiplexing

ABSTRACT

A data memory arrangement includes n columns of storage elements each column being addressable only one element at a time and having at least n 2  storage elements so as to provide a succession of square arrays. Each square array comprises square sub-sections. On storage of a complementary array of data the data is multiplexed from each square array to the next within each sub-section and after each cycle of such multiplexing the sub-sections are rotated one step cyclically. Such rearrangement of data gives freedom and speed of simultaneous access to data words occurring in original rows and/or columns without excessive penalty in the complexity of the addressing system.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a memory arrangement for data storage andretrieval, that permits words (n bits of information) to be accessed(stored or retrieved) in a variety of different modes.

2. Description of Related Art

Conventiotally, data is stored in digital integrated circuits ascontiguous words, each word having a single unique address. In certainapplications it is required to access data from common bit locations ofdifferent, but regularly spaced words (e.g. the 5th bit of every 16thword). Normally this would be achieved by a masking operation carriedout by a processor connected to the memory, but this is highlyinefficient in terms of data retrieval, since it requires `n` memoryaccesses to read (or write) n bits of data, together with the necessaryaddress generation and masking operations to be carried out by theattached processor.

SUMMARY OF THE INVENTION

It is an object of this invention to provide a data storage/retrievalsystem in which this inefficiency is at least partly overcome, and inthe preferred, general, case, to provide that `n` bits of data can beaccessed simultaneously from the rth bit location of a selected set of nwords, spaced by n^(m-1) (where the mode "m" is greater than or equal to`0`. When m=0, words are accessed in the conventional manner). Thus, inthe three dimensional case, data can be thought of as being arranged incubic n×n×n data arrays, such that any row (x word, mode=0) or anycolumn (y word, mode=1) or any z word (mode=2), may be addressed in thenormal manner, together with a mode instruction, (there being n² xwords, n² y words and n² z words in each such cube).

According to the present invention, a data memory arrangement includes asquare array of storage elements arranged in rows and columns, eachcolumn being addressable one storage element at a time, means forstoring data in the memory arrangement so that data bits of originallythe same bit position in respective row data words are storedexclusively in different columns, and means for accessing simultaneouslythe bits of a selected data word distributed over the columns of thearray.

The arrangement preferably comprises a plurality of square arrays,corresponding columns of which are addressable as single columns, onestorage element at a time, and means for addressing simultaneously aselected storage element in each such column in a plurality of modessuch that the accessed data word comprises an original row data word, anoriginal column data word of adjacent data bits or a data wordcomprising periodically spaced data bits of an original column.

There may be included rotation means effective on storage of an array ofdata bits in a square array to displace the row data words with respectto their bit positions progressively and cyclically from each row to thenext.

Where such a memory arrangement comprises n storage elements in each rowand n^(d-1) storage elements in each column, d being a dimension integergreater than two, within each block of n adjacent square arrays therotation means may be arranged to displace the whole of the data to bestored in each square array by one row bit position progressively fromeach square array to the next to provide a third dimension access todata words the bits of which lay in corresponding locations insuccessive square arrays of the original data array.

The rotation means may be arranged to displace the whole of the data tobe stored in each sub-array of n^(m) storage elements, where 3<m<d, byone row bit position progressively from each such sub-array to the nextto provide (m+1)th dimension access to data words the bits of which layin corresponding locations in successive said sub-arrays of the originaldata array.

In an alternative embodiment there may be included multiplexing meanseffective on storage of an array of data bits of word length n, where nis a power of 2, in a square array of n² storage elements, to rearrangethe bit positions of successive row words in such manner that, if eachrow word is considered in single bits, pairs of said single bits,quadruple groups comprising said pairs, etc, then the single bits withineach pair, the pairs within each quadruple group, the quadruple groupswithin an octal group, etc, are interchanged or not in any particularrow in accordance with the digits of the binary numbers from 0 to n-1attributed to the rows, the least significant digit indicating theinterchange of single bits, the next least significant digit theinterchange of pairs of bits, and so on.

Where there are n^(d-1) storage elements in each column, d being adimension integer greater than two, within each block of n adjacentsquare arrays, the multiplexing means maybe effective on storage of adata array of n^(d-1), n-bit words to rearrange the order of the rowwords in each square array in such manner that, if each square array isconsidered in single rows, pairs of said single rows, quadruple groupscomprising said pairs, etc, then the single rows within each pair, thepairs within each quadruple group, the quadruple groups within an octalgroup, etc, are interchanged or not in each square array in accordancewith the digits of the binary numbers from 0 to n-1 attributed to thesquare arrays respectively, the least significant digit indicating theinterchange of single rows, the next least significant digit theinterchange of pairs of rows, and so on.

The arrangement may comprise data multiplexing and rotation meanseffective on storage of an array of data bits in a square array torearrange the data array by a combination of cyclic rotation of groupsof data bits and interchange of groups of data bits.

Where there are n^(d-1) storage elements in each column, d being adimension integer greater than two, the data multiplexing and rotationmeans may be effective to rearrange the data array on storage such thatsquare sub-sections of a square data array are multiplexed within eachsub-section, the sub-sections are subjected to progressive cyclicrotation, and successive ones of the square arrays are subjected tomultiplexing and progressive rotation alternately.

In addition to the above general rearrangement of data, the rotationmeans may be effective in response to a rotation control signal toimpose a further rotation on the data of any accessed word.

Again, address modification means may be effective in response to aboundary shift control signal to modify the address of a word in adimension (d-1) in such manner as to access a word which extends acrossa boundary between adjacent n^(d-1) arrays in an overall n^(d) array.

It may be seen that a memory arrangement according to the presentinvention may, in a preferred embodiment, be seen as a multi-dimensionalmemory comprising a rectangular array of memory or storage elementsarranged in rows and columns, there being n storage elements in eachrow. The whole memory comprises a number of square arrays each having acapacity of n words (row, or `x` words) each word of n data bits.

The rows may be seen to constitute a first dimension, and the columnswithin a square array a second dimension. If the word length ismaintained at n bits, a third dimension may be seen to lie in wordswhich have one bit in each adjacent one of n square arrays in acorresponding position in the square array. Thus a third dimension wordmay comprise the 5th bit of the 2nd row word in each of n consecutivesquare arrays. A three-dimensional array would thus comprise n squarearrays (or layers), each of n² elements. A three-dimensional array thuscomprises n³ elements and may be considered as a cube.

The concept of further dimensions in a physically two-dimensionalrectangular array may be extended by consideration of one storageelement in one n² layer and corresponding storage elements in n² layersspaced at intervals of n layers, i.e. one element in each of nsuccessive three-dimensional `cubes`.

Similarly, a d-dimension word is provided by consideration of an arraytotalling n^(d) elements, consisting of n arrays each of n^(d-1)elements the accessed d-dimension word comprising one bit from each ofthe n arrays.

It will be appreciated that in the above consideration ofmulti-dimensional memories, the accessed words of concern, of all butthe first. dimension (the row, or `x` word), fall exclusively in thesame overall column and thus are conventionally accessible only in nseparate access processes.

The present invention resolves this difficulty by rearrangement onstorage of an original data array so that, irrespective of the dimensionof the accessed word, the bits of the word fall exclusively in differentcolumns.

There are two broad approaches to such rearrangement; (a) by rotation ofdata words and (b) by a form of multiplexing or permuting of data words.

In the general case, multi-dimensional access of a memory array of thekind referred to can be achieved by sympathetically modifying the orderin which bits of data are stored and the manner in which the memorycells are addressed, as a function of both the given address and themode instruction. In the two-dimensional case, for example, where thememory cells are arranged in square, n×n arrays and means are providedfor separately addressing each column of the arrays (so that a row dataword is addressable by a common address applied to each column), meansare provided for storing row data words in a mutually displaced relation(so that data bits of originally the same bit position in a data wordoccur exclusively in different columns). This arrangement is then suchthat a column of data bits of originally the same bit position can beaddressed simultaneously by appropriately modified row addresses appliedto the separate columns of the memory array.

One method mentioned above for storing row data words in a mutuallydisplaced relation is that of progressive and cyclic rotation withrespect to their bit positions and address prior to storage in thearray. The rotation means is then operable under the control of the modeand the address and is also such that the opposite rotation, (to thatapplied on storage) is applied on retrieval of a data word.

The multi-dimensional memory so arranged for simultaneous access can beindefinitely extended by progressively and cyclically rotating eachn^(d) array (which, if d is greater than 3, can be seen as a `d`dimensional hypercube), and appropriately modifying the separate memorycolumn addresses to access the n bit word in the mode demanded. Forexample, an n⁴ array consists of n, n³ arrays, with each n³ array havingan extra 1 bit rotation imposed on it, than the one before it, so thatthe first row word of the first n³ array has no rotation, the first rowword of the second n³ array has a single bit rotation, the first rowword of the third n³ array has a two bit rotation, and so on until thefirst row word of the nth n³ array has an (n-1) bit rotation. Thisallows a single bit to be accessed for each of the n, n³ arrays to forma word that would have been constituted by every n³ th bit in the samecolumn of the memory array had no rotation taken place and hence wouldhave been inaccessible in a single memory cycle.

In summary, it is emphasized that the multi-dimensional access memory isunderstood in terms of both its conceptual function and its actualoperation. Conceptually, for an n^(d) data array, n^(d-1) words areaddressable in "d" different modes, which for the first three modes (0,1, 2) may be equated geometrically to the x, y and z dimensions, afterwhich it is easier to think in terms of accessing words composed fromsingle bits, in the same column, of row words occurring every n^(d-2)rows. In contrast, the actual operation, involves the distribution of ann^(d) data array across n×n^(d-1) memory cells in such a way that wordsare, for example, progressively and cyclically rotated (one of manypossible permutations) so that either common or modified addresses maybe applied to the n columns of physical memory to access the data wordsin the mode demanded.

Two optional extensions to the multi-dimensional access memory are alsoconsidered, since they further utilise means for data rotation andaddress modification where these exist esentially. The first is that ofapplying an extra rotation to the data retrieved from memory underexternal control of a bit rotation control word. The second is that ofapplying an offset to the address, so that the highest dimensional words(mode=d-1) can be accessed across the boundaries of an n^(d) data array,under external control of a boundary shift control word. Both extensionshelp reduce the computational load on any external data processor towhich the multi-dimensional access memory can be attached, and thisleads to more efficient computation. However in performing the boundaryshift one restricts the boundary shift to the highest dimension, (sincethe added rotation of consecutive lower order arrays required foraccessing the lower dimensions leads to conflicting requirements interms of bit addressing).

BRIEF DESCRIPTION OF THE DRAWINGS

Several embodiments of the multi-dimensional access memory in accordancewith the invention will now be described, by way of example, withreference to the accompanying drawings, of which

FIG. 1 is a block diagram of a conventional single dimensional accessmemory;

FIG. 2 is a block diagram of a two-dimensional access memory;

FIG. 3 illustrates the disposition of data stored in a two dimensionalaccess memory in accordance with a rotational data rearrangement;

FIG. 4(a) and 4(b) are a diagrammatic illustration of the accessing ofrow and column data in the arrays of FIGS. 2 & 3.

FIG. 5 is a conceptual representation of a three-dimensional data array;

FIG. 6 is a diagram to illustrate rotational displacement of data in athree-dimensional access memory;

FIG. 7 illustrates a typical multi-dimensional access memory withoptional added rotation and boundary change facilities;

FIGS. 8(a), 8(b), 8(c) and 8(d) summarize the conceptual modes of accessof a multi-dimensional memory;

FIG. 9 shows an 8 bit (i.e. n=8) example of a fully rotatedmultidimensional access memory (MDAM) data format;

FIG. 10 shows a schematic diagram of an implementation of afull-rotate-format MDAM;

FIG. 11 presents an example of the basic modification pattern used in a16-bit full-rotate-format MDAM:

FIG. 12 shows an 8-bit example of a fully multiplexed MDAM data format;

FIG. 13 shows a schematic diagram of an implementation of afull-multiplex-format MDAM;

FIG. 14 shows an 8-bit example of a partial rotate-partial multiplexMDAM data format;

and FIG. 15 shows a schematic diagram of an implementation of a partialrotate-partial multiplex MDAM.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 1, this shows a conventional single dimensionalaccess memory in which n memories 1, 2, 3 . . . n, each 1 bit wide by Nbits long, are addressed by a common address line 3. Thus an n bit dataword can be accommodated in any row of the n×N memory array, thecomplete row word is identified and addressed by number index (M) of thestorage element employed in each 1×N memory array. The diagram shows aparticular row `M` being addressed. Each element (`a`) of the data inthe n×N memory data array is identified by the number of the elementwithin the column (`M`) and the number of the column (`r`). Since theaddress of each element of the selected row is the same (`M`), a commonaddress line 3 is used. A common control line 5 determines whether thememory access process is one of storage (a `write`) or one of retrieval(a `read`). The data elements map directly (isomorphically) into thememory storage elements.

Clearly, a data word can be extracted from any row at will, but becauseof the selective nature of the addressing facility within each memoryarray, i.e. the ability to select one, and only one, memory elementwithin a column, which facility is inherent in conventional memoryarrays, a column data word cannot be read in a single step.

One embodiment of the invention which overcomes this difficulty is shownin FIG. 2. The 1×N memory arrays 1 to n are similar to those of FIG. 1and are also addressed only on a selective basis. However in this casethe individual addresses can be applied in common, to address aparticular row `M`, as before, or, under the control of addressmodifiers 7 can be directed to progressively different (i.e. staggered)locations in each column.

Two control inputs are now required: the read/write control input 5 asbefore, to control `read` or `write` and an additional row/column, ormode control input 9 to determine a `row` or `column` mode.

In operating this arrangement the data is stored in a modified way. Datawords which are supplied a row at a time, from an original rectangulardata array, are displaced progressively and cyclically with respect totheir bit positions as shown in FIG. 3. The first row word `a11, a12, .. . a1n` is entered normally. The second row word `a21, a22 . . . a2n`is shifted to the right cyclically (`rotated`) so that the leastsignificant bit of the word, `a2n` occupies the most significant storagelocation. The remaining row words are rotated in a similar manner sothat progressively the bits that would have occupied a single 1×N memoryarray now occupy the diagonal formation such as that shown. Theessential feature is that data bits having originally the same bitposition in the various row data words, occur, after the rearrangement,exclusively in different columns. Every original column data word of nbits is thus distributed over n columns and can be addressed in a singleoperation since each 1×N memory array contains only one bit of theoriginal column word. It should be noted that the rows have beendescribed as extending from 1 to n, left to right. It is moreconventional to use a right-to-left increasing format but the principleis unaffected. Similarly, data displacement may equally be to the left.

It will be apparent that to achieve the above distribution of a columndata word it is not essential to rotate successive row wordssystematically as described above. Any set of n mutually exclusivepermutations (together with their n inverses) would be adequate; forexample successive rotations may be multiples of one column or may evenbe random, as long as the condition is maintained that no columncontains more than one of the original column bits and also that thepermutations (e.g. rotations) are recorded so as to permit reversion(application of the inverse permutation) to the original format, as willbe explained.

If the length of a 1×N memory array (a column of memory) is greater thanthe length of a data word (i.e. N>n) then a whole column cannot bedistributed for simultaneous access. However, sub-columns, each thelength of a row word (i.e. n bits long) can be addressed so that thewhole column is accessed as a sequence of sub-columns--thus requiringN/n access operations. This is illustrated in FIGS. 4(a) and 4(b) whichshow respectively the layout of row data words and column data wordswhen 8-bit column data words are stored after rotation in a 4-columnarray, i.e. N=8 and n=4. Each block of data, B1, B2, illustrated,comprises a square array, or layer, of rows and columns of four bitseach (i.e. n=4), the number of blocks or layers depending upon theoriginal column length and being typically many thousands for currenttechnology integrated circuits (e.g. dynamic RAMs).

To return to FIG. 2, the above bit-position shift of row data words isperformed on storage and retrieval by means of a `barrel shifter` or`rotator` circuit 11. On data storage into the memory array a row wordof n bits is supplied to the rotator 11 in parallel and, under thecontrol of the address line 3, a cyclic shift to the right is effectedto an extent dependent on the address of the row. A row word to bestored in the 5th row is given a shift of four bit positions and so on,in accordance with the scheme depicted in FIG. 3.

The read/write control input 5 and mode control input 9 operate asfollows. The read/write input 5 is connected to the individual memoryarrays 1 to n to effect read-out write-in in the usual way. It is alsoconnected to the rotator 11, to determine a rightwards shift on a`write` instruction and a leftwards shift on a `read` instruction. Themode control input 9 is connected to the rotator 11 to enable rotationaccording to a row or a column instruction. It is also connected to eachof the address modifiers 7 to enable or inhibit address modification incorrespondence with a column or a row instruction. In a storageoperation for a row data word, the read/write control input 5 applies a`write` signal to the rotator 11, dictating a rightwards shift. The modecontrol input 9 applies a `row` signal so producing no addressmodification. The address input 3 applies the row address, i.e. `M`, tothe (now ineffective) modifiers 7, and also to the rotator 11 todetermine the extent of the left/right shift that the rotator imposes.The row data word is thus entered into the array with a bit-positiondetermined by the rotator and into the row having address `M` specifiedby the address input 3.

In a retrieval, or `read`, operation to extract a row word in itsoriginal form, the control input 5 applies a `read` signal to therotator 11 to effect a leftwards shift. Again the mode control input 9applies a `row` signal which produces no address modification by themodifier 7, and the address input 3 specifies row address `M` andcontrols the extent of the leftwards shift of the rotator 11.

The retrieval operation is thus the inverse of the storage operation andthe originally stored row word is reproduced with the original,undisplaced, bit positions. There is, of course, no particular merit inthis form of row-word retrieval, it is merely necessary as a result ofthe bit-shifted storage process.

However, if a column word is required to be retrieved from the originalarray of row words (as the array would have been without bit-positionshifting) the process is as follows (a column word being a wordcomprising the data from the same bit position `r` in all the originalrow words). A column address (r) is applied to address input 3, a`column` instruction to mode input 9 and a `read` instruction to`read/write` control input 5. The address modifiers 7 operate on theapplied address under the control of the `column` instruction from themode control input 9 to modify the address in such a way that successive1×N memory arrays 1 to n receive successive row addresses starting withrow 1 at memory array r, row 2 at array (r+1), row 3 at array (r+2), andso on cyclically to row n at array (r-1). A particular `cyclic diagonal`is thus identified. Retrieval from these `diagonal` locations thenoccurs and the data word is passed to the rotator 11 which, undercontrol of the column address 3 applies the appropriate rotation toensure that the bit from row 1 is in the least significant (LS) bitposition. The required column data word is thus provided in its originaland correct bit position at the output of the rotator 11.

Owing to the inherent symmetry of the design, it is also possible tostore a column word, the process being as follows. A column data word isdistributed over the parallel inputs of the rotator. A column address isapplied to address input 3, a `column` instruction to mode control input9 and `write` instructions to `read/write` line 5. Each address modifier7 operates on the applied column address under control of the `column`instruction to modify the address in such a way that successive 1×Nmemory arrays 1 to n receive successive `row` addresses thus identifyinga particular `cyclic diagonal`. Storage at these diagonal locations thenoccurs, the data word first being passed through the rotator 11 underthe control of the address line 3 to apply appropriate rotation for theLS bit to be placed in the diagonal at row 1. The designated column dataword is thus stored in the memory array in its defined `cyclic diagonal`form.

The actual address modification is a simple modulo arithmetic operation(n.b. modulo arithmetic is sometimes termed `clock arithmetic`, becauseof its cyclic nature--e.g. 13 mod (12)=1, 6 mod (7)=2 etc). Sucharithmetic can readily be implemented using electronic devices such asPROM (programmable read only memory) look-up tables or alternatively asmodulo `n` adders in programmable array logic (PAL).

In mathematical terms, a square n×n memory array, represented by n, 1×nmemory arrays (A₁ . . . A_(n)) is accessed in the column mode as:

A₁ ((n-r) mod(n)), A₂ ((n-r+1) mod(n) . . . A_(n) (n-r+(N-1)) mod(n)

where `r` is the column address (o≦r<n). For example, column 3 of a 4×4memory array will be accessed as:

A₁ ((4-3) mod (4)), A₂ ((4-3+1) mod (4), A₃ (4-3+2) mod (4)) A₄ ((4-3+)mod(4))

that is:

A₁ (1), A₂ (2), A₃ (3), A₄ (0)

which may also be represented by the address modification "look-up"table shown below:

    ______________________________________                                                0    1     2      3   memory/column number                            ______________________________________                                        original                                                                              0     0      1   2    3                                               column  1     3      0   1    1                                               address 2     2      3   0    1           accessed                                    3     1      2   3    0           address                             ______________________________________                                    

When a rectangular, n×N memory array is used, where N=p.n, then the sameaddress modification is used for the p, n×n square sub-arrays; eachsub-array is indexed by (M-Mmod(n)), where M is the row address withinan overall column (0≦M<N) and Mmod (n) is the row address within acolumn of a sub-array. If n=2^(s), where s is an integer, then(M-Mmod(n)) is simply generated by taking the most significant bitsabove the s least significant bits.

By means of the above described modification permitting row and columnread out, the conventional one-dimensional access memory of FIG. 1 hasbecome a two-dimensional access memory in the sense that there are twoways in which data words can be selected from the memory, where eachaccessed data word is a simultaneous selection of data bits. In such amemory it may be seen that the additionally accessible data word isprovided by `rotating` the data in memory and then `rotating` theaddresses.

The access of data words from a memory having the form of a rectangulararray of rows and columns may be extended into higher `dimensions` thanthe above two-dimensional rows and columns. A dimension in this contextof an array of original data `n` bits wide and `N` bits long, may beconsidered as a selection of data bit locations which form a repeatablepattern in the original array. The conventional `dimension` is a row,i.e. one bit having the same row address in each column. A column is thenext simplest selection and `dimension` but this requires displacementin accordance with the invention, e.g. as in FIGS. 3 & 4 in order toovercome the difficulty that two bit locations in the same column cannotbe accessed simultaneously.

FIG. 6 illustrates a further `dimension` which consists of every fourthbit location in a column of the original array, these selected bitsbeing shifted according to the scheme of FIG. 6 to ensure that they donot fall in the same column.

The letters `A` represent all the bits of the original first column ofdata prior to storage and bit rotation. The letters B, C & D similarlyrepresent the original second, third and fourth columns. Clearly, inFIG. 6, a simple, cyclic, one-bit shift for every row would bring allthe selected bits back into the same column and thus make the wordinaccessible in a single operation.

The memory of FIG. 6 may be represented as an `n`×`n`×`n` cube as shownin FIG. 5, in which case the selected word, of every fourth or rather,every nth bit, in an original column, may be seen as a `z` wordextending along a slant line (A A A A, from n×n layer to n×n layer) in athird dimension (the first and second dimensions being the rows andcolumns). Since the layer pattern repeats after every n layers, if theoriginal column length, i.e. N bits, is greater than n², a data wordcomprising every nth bit of an original column cannot be accessed in oneoperation, but has to be accessed in groups each producing n bits.

It will be appreciated that the three-dimensional cube representation ofFIG. 5 is purely an aid to understanding, the physical layout being infact in the same form as for the two-dimensional access memory exceptthat the address modification and rotation facilities are extended towork across `n` square arrays i.e. over N rows.

The storage of data in accordance with FIG. 6 is achieved byprogressively and cyclically commencing each n×n square array (nconsecutive memory words) with an extra cyclic shift relative to theprevious square array, as is shown in FIG. 6. In FIG. 6, for the sake ofsimplicity only a four bit system is illustrated, but it will be clearthat in principle n can take any value, normally a power of two. Inaddressing a particular "z" word, the word address and the mode (=2)determines the required address modification--so that, starting with thememory element that contains the first bit of the selected "z" word andprogressing cyclically the address modification units cause incrementsof size `n` in the applied addresses.

The extent of address modification increases linearly with respect tocorresponding increases in memory dimensions. That is, for simultaneousaccess of n data bits in any one of d dimensions where d<n and n=2, 4,8, 16 etc, then (d-1) log₂ (n) binary address lines need to be modified.Also, the number of binary control lines to define the access modeincreases logarithmically and requires log₂ (d) binary control lines tobe included.

In regard to the two optional extensions (mentioned previously) of theinvention. The extension to perform an added rotation on data read from(or written into) multi-dimensional access memory is implemented simplyby employing a modulo adder to appropriately modify the rotationassociated with a particular address and mode. The optional cyclic shift(rotation) therefore requires an extra: log₂ (n) binary rotation controllines to be included.

The extension to perform a boundary shift on the highest dimension ofthe multi-dimensional access memory is implemented simply by employingmore complex address modification circuitry that allows an addressboundary to be straddled. In practice this requires control of the nextmost significant address line by means of either a PROM "look-up" tableor PLA (programmable logic array) adder system, under the direct controlof the boundary shift control word. The optional boundary shifttherefore requires an extra log₂ (n) binary boundary control lines (21,FIG. 7) to be included, if one assumes only forward shifts. Thus atypical multi-dimensional access memory will be configured as shown inFIG. 7, where the means for rotation (11) and address modification (7)have been extended to allow for supplementary rotations and boundaryshifts.

FIGS. 8(a), 8(b), 8(c) and 8(d) show the progression multi-dimensionalaccess memory from the conventional one-dimensional access memory to thefour-dimensional access memory, the effects of the optional boundaryshift also being illustrated.

In mode O (FIG. 8(a)) the store 25 is arranged as 64k, 16 bit row (`x`)words, 16 binary address lines being required to access memory. Theoptional boundary shift (1) would under these one-dimensionalcircumstances, apply at the row bit level, so that the last 16-(1) bitsof the addressed word would combine with the first 1 bits of the nextconsecutive word.

In mode 1 (FIG. 8(b)) the store 25 is arranged (conceptualised) as 4K,16×16 data arrays 29 from which row (x) or column (y) words can beaccessed, 17 binary address lines being required to distinguish any rowor column address (assuming mode control to be included in the address).The optional boundary shift (1) would under these two-dimensionalcircumstances apply at the column bit level, so that the last 16-(1)bits of the addressed column word would combine with the first 1 bits ofthe column word in the next 16×16 array 29.

In mode 2 (FIG. 8(c)), the store is arranged (conceptualised) as 256,16×16×16 data arrays 31 from which row (x) or column (y) or (z) wordscan be accessed, 18 binary address lines being required to distinguishan x, y or z address. The optional boundary shift (1) would under thesethree-dimenional circumstances apply at the z level, so that the last16-(1) bits of the addressed z word would combine with the first `1`bits of the next consecutive z word in the next 16×16×16 array 31.

In mode 3 (FIG. 8(d)), the store is arranged (conceptualised) as 16, 16⁴data arra which x, y, z or `hyperblock` (h) words can be accessed, 18binary addresses still being sufficient to distinguish any x, y, z or hwords. The optional boundary shift now extends across consecutivehypercubes.

It may be seen that in order to effect a boundary shift, the accessedword must be of a dimension lower than the highest dimension available.Thus in an n³ array the highest dimension word that can be accessedacross a boundary is a second-dimension word.

It may be noted that from a user viewpoint, the labelling of dimensions(e.g. x, y, z etc) is largely arbitrary, but once chosen it is advisableto adhere rigidly to them in order that controlling software may beconsistent.

The main application of the invention is in the performing of repetitivedata manipulation tasks (in conjunction with a processor) which involvethe movement of bits of data between or within words. For examplesuppose it is required to list, over a field of 1024 words, that the 7ththe 5th and the 0th are all `1's` and to indicate this fact by settingthe 15th bit to `1`. Conventionally this would require ANDing the entire1024 words with the mask (0000000010100001) and then comparing(subtracting) the result with the mask, which, if the same, would resultin the 15th bit of the original word being set. Employing an MDAMaccording to the invention however, the 7th, 5th and 0th bits could be"ANDed" together 16 a time in y-dimension (i.e. as column words) and theresult written into the 15th bits in parallel in the same mode. Thus theformer method would require a minimum of 1024 reads+considerableprocessing+an unknown number of writes (<1024), whereas the latter wouldtake 192 reads+128 ANDs+64 writes. Clearly, the MDAM is many times moreefficient and for a typical computer system this type of bitmanipulation would result in a throughput improvement by a factor of atleast 8.

Alternative data storage formats may be utilised, the applicability andefficiency of which are dependent upon memory speed, space and powerconstraints, and the requirements for extra shift and boundarystraddling facilities.

In general, a simplification of the addressing function (i.e. areduction in the total number of address lines) will result in a morecomplex or extended data path, and vice-versa.

The available data formats range from the fully progressive cyclicrotation mechanism described above, to a fully multiplexed structure,through any combination of rotation and multiplexing.

As a broad comparison the various formats can be summarised as follows:

The full rotation mechanism requires a large number of derived modifiedaddress lines, using a complex derivation structure. The data path must,by definition, contain a data rotator, which is then simply adapted forextra shift functions, with little timing penalty.

The fully multiplexed mechanism requires a minimum, simply derived setof modified address lines. If no extra shift function is required thenthe data path is a relatively simple set of multiplex stages. Extrashift functions necessitate a completely independent rotator, however,involving increased delay.

A combination of rotation and multiplexing may be utilised to give adata storage format which is a compromise, using a minimal to medium setof modified lines with minimal complication and delay in the data path,extra rotation inclusive.

Embodiments of these various data formatting techniques within anoverall multidimensional access memory will now be described, withreference to FIGS. 9 to 15 of the accompanying drawings.

In the following consideration the input address, that is, the addressof the required word in the original data array, is assumed to be in theform A_(x) -A_(o) (MS-LS), and will be arranged in sub-sections ofdecreasing significance left-to-right for selective manipulation forvarious dimensional access.

For first dimension access the whole input address is used directly asthe normal physical address.

For second dimension access the least significant sub-section definesthe required y word, the higher order sub-section pointing to therequired n² layer.

For the third dimension access, the least significant sub-sectiondefines the required physical (x word) location within each layer: thesecond least significant sub-section defines the required z word: andhigher order sub-sections indicate the required block of n layers of n²words per block.

For fourth dimension access the LS and second LS sub-sections indicatethe required physical (x word) location within the block of n layers.The third LS sub-section indicates the required fourth dimension word,while higher order sections point to the required set of blocks oflayers.

The address function of the various sub-sections continues similarly forhigher dimensions.

The fully rotated format illustrated by an 8-bit array in FIG. 9,utilises an additional one-bit shift for each successive word stored inphysical memory (30, FIG. 10), together with a further additional shiftbeing introduced at modulo `n` intervals, i.e. between the layers,(where n is the word length). This format allows any first dimensionword to be directly accessed (without address modification but with datarotation). Furthermore, with appropriate address modification and datarotation higher dimensional access is achieved. The second dimension isaccessed by extracting the corresponding kth bit from each of nconsecutive words, i.e. the successive bits in the kth column of theoriginal array. The third dimension is accessed by extracting the kthbit from each of n row words spaced at n row word intervals. In generalthe mth dimension is accessed by extracting the kth bit from each of nrow words spaced at n.sup.(m-2) intervals (except where m=1 which is 1stdimensional single word access). It is assumed here that access does notstraddle a (modulo n)^(m-1) word boundary e.g. second dimensional accessis from a layer of words within a row word address boundary Ar, where:n×(x)<Ar<n×(x+1) and x is an integer. A diagram of an MDAM arranged fora full rotation format is given in FIG. 10 in which componentscorresponding to those in earlier configurations are similarlyreferenced.

For an m dimensional memory of word length n, the addressing derivationis a function of the summation of (m-1) input address sections each oflog (n) digits.

For example for a 16 bit three-dimensional memory two four-bit addresssections A₇₋₄ and A₃₋₀ are required. Modified addressing may then bederived, in summation circuit 35 and modifier 7, as a functionf(Σ[(A₇₋₄)+(A₃₋₀ ]) i.e. the summation, ignoring overflow carry, of two4-bit address sections. For simplicity this will be referred to asf(Σ_(3-o)), Σ being a four-bit resultant.

The addressing mechanism is provided by a rotating binary pattern,which, for a fully rotated format, is shown in FIG. 11. The pattern maybe considered as being stored in a 16 stage cycling shift register, eachstage being tapped to provide a 4-bit address code to select a bit in aparticular column as indicated above the address codes. The pattern iscycled to a phase position according to the number of the seconddimension word to be accessed so that each 4-bit address accesses onebit of the word. Programmable logic circuitry is in fact used to achievea similar result.

The pattern shown in FIG. 11 is required for a fully rotated data formatbut in the case of a multiplexed format some of the 4-bit addresses willbe identical and an economy of address lines will result.

As may be seen from FIG. 11, the codes are the same for correspondinglines but have a progressively shifted origin according to bit positionin the basic n bit word length. The address thus becomes a f(Σ-R_(r))where Σ is the sub-section address summation, R_(r) is the RAM, i.e.column or bit number in the range 0≦r<n-1.

Thus for memory bit 0 (i.e. column 0, the LS bit) the origin (word 0) isat the right hand column of FIG. 11. Thus to address the first word inmemory (2nd dimension), Σ3-0-R_(o) =0 and the address pattern 0000 willbe used. For the second word Σ1-0=1 and the pattern is 1111; for thethird word, Σ2-0=2 and the pattern is 1110, and so on.

For memory device bit 1 (the next LS bit) the origin is shifted oneplace left. Thus to address the first word, Σ0-1-15 and the pattern is0001; to address the second word, Σ1-1=0, pattern is 0000; and so on.

Similarly, for successive memory devices (i.e. columns) the origin isshifted r places left (where r is the bit number range 0-(n-1), theaddresses being derived as a function of (Σ-r).

Third dimensional access operates on the next sub-section of addressesin the same manner, the first sub-section reverting to normaladdressing. Increasing dimensions operate on higher order sub-sectionsrespectively. For first dimensional access there is no modification.

Data rotation in rotor 11 is also a simple derivative of the sub-sectionsummation (35) being a Σbit shift for a write operation or an (n-Σ) bitshift for a read operation, and extra shift is easily included with anextra adder stage 37.

The number of modified address lines required rises exponentially withword length. Thus, 2A₀ bits, 4A₁ bits, 8A₂ bits, and so onprogressively, are required, up to n A(logn-1) bits where n is wordlength. Higher order bits repeat this pattern for higher dimensionalaccess.

For example, a 16 bit 3-D memory requires:

    ______________________________________                                        2   A.sub.0                                                                              4     A.sub.1                                                                            8   A.sub.2                                                                            16  A.sub.3                                                                                60 modified lines                 2   A.sub.4                                                                              4     A.sub.S                                                                            8   A.sub.6                                                                            16  A.sub.7                                    ______________________________________                                    

The simplest, conceptually, implementation is an adder/lookup promcircuit, but complex multiplexing may be used for higher speed.

It is assumed above that the data rotator 11 uses uni-directional shiftonly. A bi-directional shifter could be used.

The direction of shift may be reversed with a corresponding change ofthe address patterns, and shift control. To the outside world thedirection of shift is irrelevant.

The fully multiplexed format utilizes a simple multiplexing mechanism toachieve data distribution. For each successive word in physical memory,a higher order stage of multiplex shift/flip is introduced, with afurther additional stage being introduced at modulo n word boundaries,as depicted in the example of FIG. 12. Thus, for the first word, data isstored normally. For the second word a first multiplex stage isintroduced which flips, i.e. interchanges, single word bits 1-0, 3-2,5-4 and so on. For word 2 a second stage multiplex is introduced (thefirst stages reverting to normal) which flips pairs of bits 3&2 with1&0, 7&6 with 5&4 and so on. For the third word, both first and secondstage multiplex is introduced and quadruple groups are `flipped` orinterchanged. Higher order stages flip more bits respectively; thesystem is only sensible for a 2^(a) bit wide memory, a being integer.

For third-dimensional access, the first word of each successive layer isflipped with an additional stage of multiplex being engaged in a similarmanner to the consecutive words of the first layer.

No data rotation is required with this format. The write multiplexingmust be the converse of read multiplexing, however. Additional shift(input 42) must be applied, as shown in FIG. 13, using a completelyseparate data rotator 11.

For an m dimensional memory of word length n the addressing derivationis again a function of the individual bit summations of multiple addresssections, of length log(n), and a fairly simple set of multiplexersdriven by the adder outputs, to select true or inverse input addresses.Thus only two lines for each input address need be derived, aconsiderable saving for large n when compared against the full rotateformat.

For first dimensional access all address bits will follow thecorresponding input address.

For second-dimension access the LS sub-section of addresses will bemodified according to the summation result. If each address is formedinto two bits T₁ Ax and T₂ Ax where T₁ Ax is a first term for Ax, T₂ Axis a second term, then these address bits will be applied to the nmemory devices (columns) in a binary alternating pattern.

Thus,

T₁ A₀ is applied to devices 0,2,4,6,8 - - -

T₂ A₂ is applied to devices 1,3,5,7,9 - - -

T₁ A₁ is applied to devices 0,1,4,5,8,9 - -

T₂ A₁ is applied to devices 2,3,6,7,10,11 -

T₁ A₂ is applied to devices 0,1,2,3,8,9,10,11, - -4,5,6,7,12,13,14,15 -

and so on. This pattern repeats for each sub-section of addresses.

The addressing will then be derived such that, for second-dimensionalaccess:

    ______________________________________                                        for   A.sub.0 if    Σ.sub.0 = 0                                                                      T.sub.1 A.sub.0 = 0                                                                   T.sub.2 A.sub.0 = 1                                          Σ.sub.0 = 1                                                                      T.sub.1 A.sub.0 = 1                                                                   T.sub.2 A.sub.0 = 0                            A.sub.1 if    Σ.sub.1 = 0                                                                      T.sub.1 A.sub.1 = 0                                                                   T.sub.2 A.sub.1 = 1                                          Σ.sub.1 = 1                                                                      T.sub.1 A.sub.1 = 1                                                                   T.sub.2 A.sub.1 = 0                            A.sub.2 if    Σ.sub.2 = 0                                                                      T.sub.1 A.sub.2 = 0                                                                   T.sub.2 A.sub.2 = 1                                          Σ.sub.2 = 1                                                                      T.sub.1 A.sub.2 = 1                                                                   T.sub.2 A.sub.2 = 0                      ______________________________________                                    

and so on.

This pattern is repeated for higher order bits for higher orderdimensional access.

Implementation may be achieved with a simple set of one bit adders 39and a multiplex network, with multiplex networks 43 and 45 for the datafilm mechanism, for example as shown in FIG. 13.

In an alternative arrangement, the one bit adders 39 may be replaced bysimple logic gating in the form of multiple exclusive OR gating orsimilar, but this will get more complex for a large number ofdimensions.

The FIG. 12 arrangement represents only one of several possiblemultiplex formats; the addressing will remain similar for mostvariations.

The partial multiplex, partial rotate format, an example of which isillustrated in FIG. 14, requires that the total word length n besub-divided into sections of length 2^(a) e.g. 2, 4 or 8 bits. Thesesections are then formatted using the multiplex flip technique. Thesub-sections are then rotated around the total memory width at intervalsof 2^(a) words. This technique allows for partial simplification of themodified address derivation mechanism in conjunction with a minorcomplication and delay in the data path; it involves a rotator mechanismallowing for the inclusion of the extra shift facility with negligiblepenalty.

A schematic diagram of a partial rotation/partial multiplex is given inFIG. 15. Again, similar references indicate similar components. Thefirst word is stored normally, the second introduces a first stage flip;the third a second stage flip (first stage flip disabled) and the fourthintroduces first and second stage flip multiplexing, and so on up to alimit of 2^(a) words (sub-section length). The next word is then storedwith a rotation of 2^(a) and no flip multiplexing; the sequencecontinues for high order words up to n words.

For third dimensional access and beyond, the first word of eachsuccessive layer is stored with the same progressive multiplex/shiftpattern as for the first n words, as above.

There is a balance to be struck here between the reduction of addressderivation complexity by more multiplexing, and the increase in dataflip circuits before input to the rotator (giving extra delay). Therotator has once again become an integral part of the mechanism, thusextra shift (input 42) presents little penalty.

The address derivation is now dependent upon a multi-part summation ofaddress sub-sections using adders 38 and 47. The sub-section multiplexis controlled by a set of individual 1 bit adders 38 operating onrespective bits of the sub-section addresses and multiplex networks 43,44 and 45. The higher order/rotation addressing is controlled by a fullsummation 47 term of the remaining bits of the sub-section addresses andmultiplex stages.

Thus for a 16 bit example, the word length may be sub-dividied into 4sub-sections of 4 bits requiring 2 bits of each address sub-section forthe multiplex control 43, 44 and 45 leaving two bits to control therotate and higher order addressing in multiples of four by way ofsummation 47. Thus two one bit adders operate on A₀ +A₄ +A₈ + --- and A₁+A₅ +A₉ + --- and a full two bit adder operates on A₃,2 +A₇,6 +A₁₁,10 +---.

The LS bit derivations are then performed according to dimensionalaccess and one bit summations Σ₀ and Σ₁, etc using the pattern indicatedon the full multiplex mode. The remaining bits of each sub-section aremodified using the rotating patterns indicated in the rotating mode (thefirst remaining bit adopting the pattern detailed for the LS address ofthat mode, and so on).

For some combinations of n and a, the word length and the sub-sectionlength, the remaining bit modifications may also become a fairly simplemultiplex derivation. For instance the whole of a 16 bit 3-D derivationusing 4 bit sub-sections can be done with a simple set of adders, and abank of 2 and 4 bit multiplexers.

The total number of address lines will be ##EQU1## per addresssub-section, where 1=log(n)-log(a)

For example for a 16 bit sub-section length 4 memory, each sub-sectionmodification will require [2² +2+4]=10 lines. For 3D operation thisrequires 20 lines, which is not a great penalty when compared againstthe full multiplex (16 lines), and allows extra shift facilitiesdirectly with only a minimal flip-move delay added to the data path.

The data flip multiplexer will be controlled by Σ₁ and Σ₀ directly, thedata rotator will be controlled by 4×Σ₃.2 in the 16 sub 4 example.

We claim:
 1. A data memory arrangement comprising:(I)(a) n^(d) storageelements in rows and columns, each of said rows comprising n of saidstorage elements and each of said columns comprising n^(d-1) of saidstorage elements,(b) means for addressing each of said columns one saidstorage element at a time, (c) said d being a dimension integer greaterthan two so that said arrangement comprises n^(d-2) square arrays ofsaid storage elements, (d) each of said square arrays comprising squaresub-sections arranged in n/2^(a) sub-section rows and n/2^(a)sub-section columns, (e) each of said square sub-sections comprising2^(2a) storage elements in 2^(a) rows and 2^(a) columns, a being aninteger, (II) data multiplexing and rotation means for rearranging adata array of n^(d-1) rows of data bits and n columns of data bits forstorage in said memory arrangement--the rearrangement being such that(a)throughout each n square arrays of said memory arrangement the storageof data in said sub-sections varies from one square array to the next bymultiplex changes within each said sub-section through a multiplex cycleextending over a group of 2^(a) square arrays, (b) and after each saidgroup of 2^(a) square arrays by a rotation imposed upon the next saidgroup, said rotation being of all the sub-sections within theirrespective said square arrays, said rotation being cyclic andprogressive from one said group to the next said group, (c) and furthersuch that after n of said square arrays a said rotation is effectedwithout a multiplex change.
 2. A data memory arrangement according toclaim 1 wherein said data multiplexing and rotation means comprisesmeans for storing a first square array of data in a first of said squarearrays of storage elements and rearranging said data by multiplexingdata bits within each of said sub-section rows, according to a multiplexcycle extending progressively over the 2^(a) rows of each saidsub-section, multiplexing said sub-section rows within said first squarearray according to a multiplex cycle extending progressively over then/2^(a) sub-section rows of said first square array, rotating saidsub-section-rows horizontally and progressively, and rotating saidsub-section columns vertically and progressively.
 3. A memoryarrangement according to claim 1, further comprising means for applyinga rotation control signal to said rotation means for imposing a furtherrotation on the address of any accessed word.
 4. A memory arrangementaccording to claim 1, further comprising address modification meansresponsive to a boundary shift control signal for modifying the addressof a data word in a dimension (d-1) and accessing a data word whichextends across a boundary between adjacent n^(d-1) arrays in an n^(d)data array.
 5. A memory arrangement according to claim 1, furthercomprising addressing means for addressing locations in individualcolumns of a said square array, said addressing means comprising logiccircuitry means for storing bit location address codes for applicationto respective columns in parallel and for cycling said codes intocorrespondence with said columns in dependence upon the word to beaccessed.
 6. A method of storing a rectangular data array in acorresponding rectangular array of storage elements to permitsimultaneous access to data elements in the same column of said dataarray, said array of storage elements comprising n^(d-2) square arrays,where d is a dimension integer greater than 2, each of said squarearrays comprising n² storage elements arranged in rows and columns, andeach of said square arrays comprising square sub-sections each of 2^(2a)storage elements, a being an integer multiplexing the data elements saidmethod comprising the steps of:(I) receiving a first square array of n²data elements of said data array; (II) rearranging said first squarearray of data elements by:(a) multiplexing the data elements of each rowprogressively through the rows of each of square sub-sections of saidfirst square array of data elements; (b) subjecting said rows ofsub-sections to a multiplexing cycle; (c) rotating said rows ofsub-sections in the row direction progressively from row to row; (d)rotating columns of said sub-sections in the column directionprogressively from column to column; (III) storing said first squarearray of data elements so rearranged in a first square array of saidstorage elements; (IV) rearranging successive ones of said square arraysof data elements by:(a) subjecting sub-sections of data elements insuccessive said square arrays of data elements to respective steps of amultiplex cycle; (b) rotating said rows of sub-sections of data elementsin the row direction by one sub-section after each said multiplex cycle;(c) rotating said columns of sub-sections of data elements in the columndirection by one sub-section after each said multiplex cycle; and (V)storing the successive ones of said square arrays of data elements sorearranged in successive respective ones of said square arrays of saidstorage elements.